`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:31:24 03/28/2014 
// Design Name: 
// Module Name:    clock_divider_keyboard 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clock_divider_keyboard( up, down, clk );

input ypos_central;
input clk;
input up,down;

reg [20:0] freq_count_y;

always @ (posedge clk)
begin
	
	if (freq_count_y == 1680000)
	begin
		freq_count_y <= 0;
	end
	else
		freq_count_y <= freq_count_y + 1;
	

	if (up==1 & frequency_count_y==0)
		ypos_central = ypos_central + 1; 
	else
		ypos_central = ypos_central;
	
	if (down==1 & frequency_count_y==0)
		ypos_central = ypos_central - 1; 
	else
		ypos_central = ypos_central;
		
end

endmodule
